The ability to efficiently and thoroughly test integrated circuits is a goal for manufacturers and purchasers. The complexity of conventional testing varies widely, as does the cost, from large scale automated test equipment to testing using simple test vectors. What such integrated circuit testing systems have in common is that existing test resources are connected to a Device Under Test (DUT) as shown in FIG. 1. This configuration provides dedicated tester resources to the DUT. These resources can include a control unit, a stimulus/response system and other support functions.
Semiconductor manufacturers have tried to lower test costs by increasing the number of devices tested in parallel with the test resources. One conventional technique that has been adopted, particularly for memory devices, is the “shared resource” architecture. FIG. 2 is an illustration of a conventional shared resource architecture. This architecture connects multiple DUTs to a central stimulus/response generation unit. The DUTs then share stimulus/response signals from the system. The shared DUT pins can be either directly tied together, or they can have separate buffers (pin electronics) to isolate the DUTs.
There are various problems with the shared resource approach. First, this approach becomes inefficient when the DUTs require special testing, e.g., redundancy, programmability, etc. In many cases, adding a second DUT to a shared stimulus/response generator only increases test throughput by a factor of 1.6-1.7 (versus an expected increase of 2.0). Higher parallel testing is even less efficient. Testing four devices with a shared resource system may only increase throughput by a factor of 2.5 (versus a factor of 4.0). Much of this introduced inefficiency is due to the sharing of the single stimulus/response system and the sharing of a single control unit. Second, this architecture often results in very complicated test programs since the program must be written to insure test integrity under all perturbations of pass/fail conditions of each device. Third, there can be electrical interactions between the DUTs that negatively affect test performance and integrity.
What is needed is a system and method for testing integrated circuits (1) that enable parallel testing while providing an efficient set of resources for various applications; (2) increases the throughput of an existing test systems; (3) increases the efficiency of test controllers by having a dedicated engine that implements and coordinates the test throughput; and/or (4) uses a memory mapped environment to simplify test programs for memory devices.